Verilog programs

Half Subtractor and Full Subtractor :  (a) Dataflow modelling `timescale 1ns / 1ps module half_subtractor_dataflow(a,b,d,bo); input a,b; output d,bo; assign d=a^(~b); assign bo=(a&(~b)); endmodule (b) Behavioral Modeling `timescale 1ns / 1ps module half_subtractor_behav(a,b,d,bo); input a,b; output reg d,bo; reg [1:0]d1; reg [1:0]s1; always@* begin d1[0]<=b; d1[1]<=a; case(d1) 2'b00: s1<=2'b00; 2'b01: s1<=2'b11; 2'b10: s1<=2'b10; 2'b11: s1<=2'b00; default: s1<=2'b00; endcase d<=s1[1]; bo<=s1[0]; end endmodule (c) Structural Modeling `timescale 1ns / 1ps module half_subtractor_struct(a,b,d,bo); input a,b; output d,bo; xor21 u1(a,b,d); not1 u2(b,b1); and21 u3(a,b1,bo); endmodule module not1(a,y); input a; output y; assign y=~a; endmodule module and21(a,b,y); input a,b; output y; assign y=a&b; endmodule module xor21(a,b,y); input a,b; output y; assign y=a^b...

Universal Shift Register :  Program Code : `timescale 1ns / 1ps module univsr4bit74x194(clk,clrbar,s,lin,rin,d,q); input clk,clrbar,lin,rin; input [1:0]s; input [3:0]d; output reg [3:0]q; always@(posedge clk) begin if(clrbar==1'b0) q<=4'b0000; else begin case (s) 2'b00: q<=q ; 2'b01: q<={rin,q[3:1]}; 2'b10: q<={q[2:0],lin}; 2'b11: q<=d; default: q<=4'b0000; endcase end end endmodule

RAM :  Program Code : `timescale 1ns / 1ps module ram16x4(CLK,CS_L, WE_L, A,DI,DO); input CLK,CS_L,WE_L; input [3:0]A,DI; output reg [3:0]DO; reg [3:0] RAM [15:0]; always@(posedge CLK) begin if(CS_L==1'b0) begin if(WE_L==1'b0) RAM[A]<=DI; else DO<=RAM[A]; end else DO<=4'bXXXX; end endmodule

ALU : Program Code : `timescale 1ns / 1ps module ALU74X181(M,S,A_L,B_L,CN,CN4,F_L,P_L,G_L,AEQB); input M,CN; input [3:0]S,A_L,B_L; output reg [3:0]F_L; output reg CN4,P_L,G_L,AEQB; reg [4:0]MS; reg [3:0]F; always@* begin MS<={M,S}; case(MS) 5'b00000: F_L<=A_L-1'b1; 5'b00001: F_L<=(A_L&B_L)-1'b1; 5'b00010: F_L<=(A_L&(~B_L))-1'b1; 5'b00011: F_L<=-1'b1; 5'b00100: F_L<=A_L+(A_L|(~B_L)); 5'b00101: F_L<=(A_L&B_L)+(A_L|(~B_L)); 5'b00110: F_L<=A_L-B_L-1'b1; 5'b00111: F_L<=A_L|(~B_L); 5'b01000: F_L<=A_L+(A_L|B_L); 5'b01001: F_L<=A_L+B_L; 5'b01010: F_L<=(A_L&(~B_L))+(A_L|B_L); 5'b01011: F_L<=A_L|B_L; 5'b01100: F_L<=A_L+A_L; 5'b01101: F_L<=(A_L&B_L)+A_L; 5'b01110: F_L<=(A_L&(~B_L))-A_L; 5'b01111: F_L<=A_L; 5'b10000: F_L<=~A_L; 5'b10001: F_L<=~(A_L&B_L); 5'b10010: F_L<=(~A_L)|(~B...

Decade Counter and 4 Bit Counters are discussed in this post ... `timescale 1ns / 1ps module dec_counter_74x90( input CLK, input [1:0] R0, input [1:0] R9, output reg [3:0] q); always@(negedge CLK) begin if(R0==2'b11) q <=4'b0000 ; else if(R9==2'b11) q<=4'b1001; else if(q!=4'b1001) q <= q+1'b1; else q <= 4'b0000; end endmodule 4 Bit Counter : `timescale 1ns / 1ps module counter_74x93( input CLK, input [1:0] R0, output reg [3:0] q ); always@(negedge CLK) begin if(R0==2'b11) q<=4'b0000; else q <= q+1'b1; end endmodule

Flip Flops : D- Flip Flop and JK Flip Flop Program Code : (a) D-Flip Flop `timescale 1ns / 1ps module D_FF_74LS74(D,CLK,PR_L,CLR_L,Q,QN); input D,CLK,PR_L,CLR_L; output reg Q,QN; always@(posedge CLK) begin if(PR_L==1'b0 & CLR_L==1'b1) begin Q<=1'b1; QN<=1'b0; end else if(PR_L==1'b1 & CLR_L==1'b0) begin Q<=1'b0; QN<=1'b1; end else if(PR_L==1'b0 & CLR_L==1'b0) begin Q<=1'b1; QN<=1'b1; end else if(PR_L==1'b1 & CLR_L==1'b1) begin if(D==1'b1) begin Q<=1'b1; QN<=1'b0; end else begin Q<=1'b0; QN<=1'b1; end end else begin Q<=Q; QN<=QN; end end endmodule (b) JK Flip Flop `timescale 1ns / 1ps module JK_FF_74LS109(J,K_L,CLK,PR_L,CLR_L,Q,QN); input J,K_L,CLK,PR_L,CLR_L; output Q,QN; wire W1,W2,W3,W4,W5,W6; and x1(W1,J,CLR_L,W6,QN); and x2(W2,K_L,CLR_L,Q); nor x3(W3,W1,W2); nand x4(W4,W5,W3,PR_L); nand x5(W5,W4,CLR_L,CLK); nand x6(W6,W5,CL...

Comparator : 74 85  `timescale 1ns / 1ps module B4_COMP_74X85(A,B,AGBIN,ALBIN,AEQBIN,AGBOUT,ALBOUT,AEQBOUT); input [3:0]A,B; input AGBIN,ALBIN,AEQBIN; output reg AGBOUT,ALBOUT,AEQBOUT; always@* begin if (A[3]>B[3]) begin AGBOUT<=1'b1; ALBOUT<=1'b0; AEQBOUT<=1'b0; end else if(A[3]<B[3]) begin AGBOUT<=1'b0; ALBOUT<=1'b1; AEQBOUT<=1'b0; end else if(A[3]==B[3] & A[2]>B[2]) begin AGBOUT<=1'b1; ALBOUT<=1'b0; AEQBOUT<=1'b0; end else if(A[3]==B[3] & A[2]<B[2]) begin AGBOUT<=1'b0; ALBOUT<=1'b1; AEQBOUT<=1'b0; end else if(A[3]==B[3] & A[2]==B[2] & A[1]>B[1]) begin AGBOUT<=1'b1; ALBOUT<=1'b0; AEQBOUT<=1'b0; end else if(A[3]==B[3] & A[2]==B[2] & A[1]<B[1]) begin AGBOUT<=1'b0; ALBOUT<=1'b1; AEQBOUT<=1'b0; end else if(A[3]==B[3] & A[2]==B[2] & A[1]==B[1] & A[0]>B[0]) begin AGBOU...

Multiplexer :  74 151  `timescale 1ns / 1ps module mux_74x151(EN_L, S, D, Y); input EN_L; input [2:0]S; input [7:0]D; output reg Y; reg y1; always@* begin case(S) 3'b000: y1<=D[0]; 3'b001: y1<=D[1]; 3'b010: y1<=D[2]; 3'b011: y1<=D[3]; 3'b100: y1<=D[4]; 3'b101: y1<=D[5]; 3'b110: y1<=D[6]; 3'b111: y1<=D[7]; default: y1<=1'b0; endcase if(EN_L==1'b0) Y<=y1; else Y<=1'b0; end endmodule Demultiplexer : 74 155 `timescale 1ns / 1ps module demux_74x155(ea,eab,ebb1,ebb2,A,outa,outb); input ea,eab,ebb1,ebb2; input [1:0]A; output reg [3:0]outa,outb; reg [3:0] y1; always@* begin case(A) 2'b00: y1<=4'b0111; 2'b01: y1<=4'b1011; 2'b10: y1<=4'b1101; 2'b11: y1<=4'b1110; default: y1<=4'b1111; endcase if(ea==1'b1 & eab==1'b0) outa <=y1; else outa <=4'b1111; if(ebb1==1'b0 & ebb2==1'b0) outb <=y1; else out...

Decoder by using 74 138 Program Code :  module simpledecoder(     input [1:0] A,     output reg [3:0] O     ); always @*     begin     case(A)         2'b00: O<=4'b0001;         2'b01: O<=4'b0010;         2'b10: O<=4'b0100;         2'b11: O<=4'b1000;         default O<=4'b0000;        endcase     end endmodule Simple Decoder using DATA FLOW MODELLING 2 by 2 Decoder module simpledecoder(     input [1:0] A,     output reg [3:0] O     ); always @*     begin     case(A)         2'b00: O<=4'b0001;         2'b01: O<=4...

Encoders : 74 148 Program Code : module encoder74148(     input [7:0] I_L,     output reg [2:0] O_L,     input [0:0] EI,     output reg [0:0] EO_L,     output reg [0:0] GS     ); wire [7:0]I; assign I=~I_L; always @*  if(EI==0)  begin   if(I==8'b00000000)    begin     GS<=1'b1;     EO_L<=1'b0;     O_L<=3'b111;    end  if(I==8'b00000001)   O_L<=3'b111;   if(I>=8'b00000010&I<=00000011)   O_L <=3'b110;  if(I>=8'b00000100&I<=00000111)   O_L<=3'b101;  if(I>=8'b00001000&I<=00001111)   O_L<=3'b100;  if(I>=8'b00010000&I<=00011111)   O_L<=3'b011;  if(I>=8'b00100000&I<=00111111)   O_L<=3'b010;  if(I>=8'b01000...

Logic Gates are Two Types : Basic Gates and Universal Gates A gate is called as Universal Gate when all the basic gates can be formed by using only that gate ... Basic Gates are AND NOT OR Universal Gates are NAND NOR and many more .. Some other gates are Extra Gates which are X-OR and X-NOR gates ... Verilog Implementation of these gates are given here ! (a) Dataflow modeling `timescale 1ns / 1ps module logic_gates( input a, input b, output [6:0] y); assign y[0]=~a; assign y[1]=a&b; assign y[2]=a|b; assign y[3]=~(a&b); assign y[4]=~(a|b); assign y[5]=a^b; assign y[6]=~(a^b); endmodule (b) Behavioral Modeling `timescale 1ns / 1ps module logic_gates_behav(a,b,y); input a; input b; output reg [6:0] y; always@* begin y[0]<=~a; y[1]<=a&b; y[2]<=a|b; y[3]<=~(a&b); y[4]<=~(a|b); y[5]<=a^b; y[6]<=~(a^b); end endmodule (c) Structural Modeling `timescale 1ns / 1ps module logic_gates_struct(a,b,y); input a; in...

Ripple Carry Adder :   This means the carry is the ripple which is out from the first stage and used in the next stage .. Block diagram of RCA is Program Code : `timescale 1ns / 1ps module RCA(a,b,cin,s,cout); input [3:0]a,b; input cin; output [3:0]s; output cout; full_adder_behav1 u1(a[0],b[0],cin,s[0],c1); full_adder_behav1 u2(a[1],b[1],c1,s[1],c2); full_adder_behav1 u3(a[2],b[2],c2,s[2],c3); full_adder_behav1 u4(a[3],b[3],c3,s[3],cout); endmodule module full_adder_behav1(a,b,cin,s,cout); input a,b,cin; output reg s,cout; reg [2:0]d; reg [1:0] s1; always@* begin d[0]<=cin; d[1]<=b; d[2]<=a; case(d) 3'b000: s1<=2'b00; 3'b001: s1<=2'b10;  3'b010: s1<=2'b10; 3'b011: s1<=2'b01;  3'b100: s1<=2'b10;  3'b101: s1<=2'b01;  3'b110: s1<=2'b01;  3'b111: s1<=2'b11;  default: s1<=2'b00;  endcase s<=s1[1]; cout<=s1[0]; end endmodule

Full Adder can be implemented by using mux .... These are the possible ways to do that !

Full Adder : Full Adder contains a extra carry input when compared to Half Adder , Here we are including the Carry of the previous stage in the present stage addition . Program Code : (a) Dataflow Modeling `timescale 1ns / 1ps module full_adder_dataflow(a,b,cin,s,cout); input a,b,cin; output s,cout; assign s=a^b^cin; assign c=(a&b)|((b^cin)|(cin^a)); endmodule  (b) Behavioral Modeling `timescale 1ns / 1ps module full_adder_behav1(a,b,cin,s,cout); input a,b,cin; output reg s,cout; reg [2:0]d; reg [1:0] s1; always@* begin d[0]<=cin; d[1]<=b; d[2]<=a; case(d) 3'b000: s1<=2'b00; 3'b001: s1<=2'b10;  3'b010: s1<=2'b10; 3'b011: s1<=2'b01;  3'b100: s1<=2'b10;  3'b101: s1<=2'b01;  3'b110: s1<=2'b01;  3'b111: s1<=2'b11;  default: s1<=2'b00;  endcase s<=s1[1]; cout<=s1[0]; end endmodule (c) Structural Modeling `timesc...

Half Adder : It contains two inputs and two outputs , the inputs are those which are to be added and the outputs are sum and carry . Program : (a) Dataflow modeling `timescale 1ns / 1ps module half_adder_dataflow(a,b,s,c); input a,b; output s,c; assign s=a^b; assign c=a&b; endmodule  (b) Behavioral Modeling `timescale 1ns / 1ps module half_adder_behav(a,b,s,c); input a,b; output reg s,c; always@* begin if(a==1'b0 & b==1'b0) begin s<=1'b0; c<=1'b0; end else if(a==1'b0 & b==1'b1) begin s<=1'b1; c<=1'b0; end else if(a==1'b1 & b==1'b0) begin s<=1'b1; c<=1'b0; end  else if(a==1'b1 & b==1'b1) begin s<=1'b1; c<=1'b1; end end endmodule  (c) Structural Modeling `timescale 1ns / 1ps module half_adder_struct(a,b,s,c); input a,b; output s,c; xor21 u1(a,b,s); and21 u2(a,b,c); endmodule  module and21(a,b,y); input a,b; ou...

I am Key~Ttu and this blog contains programs related to Verilog HDL . Software used to simulate the programs is Xilinx 10.1 and the download link is already given in my home page and the programs are going to be updated here ... Happy Learning