Logic Gates

Logic Gates are Two Types : Basic Gates and Universal Gates

A gate is called as Universal Gate when all the basic gates can be formed by using only that gate ...

Basic Gates are AND NOT OR

Universal Gates are NAND NOR and many more ..

Some other gates are Extra Gates which are X-OR and X-NOR gates ... Verilog Implementation of these gates are given here !

(a) Dataflow modeling

`timescale 1ns / 1ps
module logic_gates(
input a,
input b,
output [6:0] y);
assign y[0]=~a;
assign y[1]=a&b;
assign y[2]=a|b;
assign y[3]=~(a&b);
assign y[4]=~(a|b);
assign y[5]=a^b;
assign y[6]=~(a^b);
endmodule

(b) Behavioral Modeling

`timescale 1ns / 1ps
module logic_gates_behav(a,b,y);
input a;
input b;
output reg [6:0] y;
always@*
begin
y[0]<=~a;
y[1]<=a&b;
y[2]<=a|b;
y[3]<=~(a&b);
y[4]<=~(a|b);
y[5]<=a^b;
y[6]<=~(a^b);
end
endmodule

(c) Structural Modeling

`timescale 1ns / 1ps
module logic_gates_struct(a,b,y);
input a;
input b;
output [6:0] y;
not1 u1(a,y[0]);
and2 u2(a,b,y[1]);
or2 u3(a,b,y[2]);
nand2 u4(a,b,y[3]);
nor2 u5(a,b,y[4]);
xor2 u6(a,b,y[5]);
xnor2 u7(a,b,y[6]);
endmodule 
module not1(a,y);
input a;
output y;
assign y=~a;
endmodule
module and2(a,b,y);
input a,b;
output y;
assign y=a&b;
endmodule
module or2(a,b,y);
input a,b;
output y;
assign y=a|b;
endmodule
module nand2(a,b,y);
input a,b;
output y;
assign y=~(a&b);
endmodule
module nor2(a,b,y);
input a,b;
output y;
assign y=~(a|b);
endmodule
module xor2(a,b,y);
input a,b;
output y;
assign y=a^b;
endmodule
module xnor2(a,b,y);
input a,b;
output y;
assign y=~(a^b);
endmodule