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Introduction to this Blog

I am Key~Ttu and this blog contains programs related to Verilog HDL . Software used to simulate the programs is Xilinx 10.1 and the download link is already given in my home page and the programs are going to be updated here ...

Happy Learning

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Full Adder Using Multiplexer

Full Adder can be implemented by using mux .... These are the possible ways to do that !
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Multiplexer and Demultiplexer

Multiplexer :  74 151  `timescale 1ns / 1ps module mux_74x151(EN_L, S, D, Y); input EN_L; input [2:0]S; input [7:0]D; output reg Y; reg y1; always@* begin case(S) 3'b000: y1<=D[0]; 3'b001: y1<=D[1]; 3'b010: y1<=D[2]; 3'b011: y1<=D[3]; 3'b100: y1<=D[4]; 3'b101: y1<=D[5]; 3'b110: y1<=D[6]; 3'b111: y1<=D[7]; default: y1<=1'b0; endcase if(EN_L==1'b0) Y<=y1; else Y<=1'b0; end endmodule Demultiplexer : 74 155 `timescale 1ns / 1ps module demux_74x155(ea,eab,ebb1,ebb2,A,outa,outb); input ea,eab,ebb1,ebb2; input [1:0]A; output reg [3:0]outa,outb; reg [3:0] y1; always@* begin case(A) 2'b00: y1<=4'b0111; 2'b01: y1<=4'b1011; 2'b10: y1<=4'b1101; 2'b11: y1<=4'b1110; default: y1<=4'b1111; endcase if(ea==1'b1 & eab==1'b0) outa <=y1; else outa <=4'b1111; if(ebb1==1'b0 & ebb2==1'b0) outb <=y1; else out...
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