RAM

RAM : 



Program Code :

`timescale 1ns / 1ps
module ram16x4(CLK,CS_L, WE_L, A,DI,DO);
input CLK,CS_L,WE_L;
input [3:0]A,DI;
output reg [3:0]DO;
reg [3:0] RAM [15:0];
always@(posedge CLK)
begin
if(CS_L==1'b0)
begin
if(WE_L==1'b0)
RAM[A]<=DI;
else
DO<=RAM[A];
end
else
DO<=4'bXXXX;
end
endmodule