Decade Counter and 4 Bit Counters are discussed in this post ...
`timescale 1ns / 1ps
module dec_counter_74x90(
input CLK,
input [1:0] R0,
input [1:0] R9,
output reg [3:0] q);
always@(negedge CLK)
begin
if(R0==2'b11)
q <=4'b0000
; else if(R9==2'b11)
q<=4'b1001;
else if(q!=4'b1001)
q <= q+1'b1;
else
q <= 4'b0000;
end
endmodule
4 Bit Counter :
`timescale 1ns / 1ps
module dec_counter_74x90(
input CLK,
input [1:0] R0,
input [1:0] R9,
output reg [3:0] q);
always@(negedge CLK)
begin
if(R0==2'b11)
q <=4'b0000
; else if(R9==2'b11)
q<=4'b1001;
else if(q!=4'b1001)
q <= q+1'b1;
else
q <= 4'b0000;
end
endmodule
4 Bit Counter :
`timescale 1ns / 1ps
module counter_74x93(
module counter_74x93(
input CLK,
input [1:0] R0,
output reg [3:0] q );
input [1:0] R0,
output reg [3:0] q );
always@(negedge CLK)
begin
if(R0==2'b11)
q<=4'b0000;
else
q <= q+1'b1;
end
endmodule
begin
if(R0==2'b11)
q<=4'b0000;
else
q <= q+1'b1;
end
endmodule
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