Registers

Universal Shift Register : 

Program Code :

`timescale 1ns / 1ps

module univsr4bit74x194(clk,clrbar,s,lin,rin,d,q); input clk,clrbar,lin,rin;
input [1:0]s;
input [3:0]d;

output reg [3:0]q;
always@(posedge clk)
begin
if(clrbar==1'b0)

q<=4'b0000;
else
begin

case (s)
2'b00: q<=q ;
2'b01: q<={rin,q[3:1]};
2'b10: q<={q[2:0],lin};

2'b11: q<=d;
default: q<=4'b0000;
endcase

end
end
endmodule