Flip Flops

Flip Flops : D- Flip Flop and JK Flip Flop

Program Code :

(a) D-Flip Flop

`timescale 1ns / 1ps
module D_FF_74LS74(D,CLK,PR_L,CLR_L,Q,QN); input D,CLK,PR_L,CLR_L;
output reg Q,QN;
always@(posedge CLK)
begin
if(PR_L==1'b0 & CLR_L==1'b1)
begin
Q<=1'b1;
QN<=1'b0;
end
else if(PR_L==1'b1 & CLR_L==1'b0)
begin
Q<=1'b0;
QN<=1'b1;
end
else if(PR_L==1'b0 & CLR_L==1'b0)
begin
Q<=1'b1;
QN<=1'b1;
end
else if(PR_L==1'b1 & CLR_L==1'b1)
begin
if(D==1'b1)
begin
Q<=1'b1;
QN<=1'b0;
end
else
begin
Q<=1'b0;
QN<=1'b1;
end
end
else
begin
Q<=Q;
QN<=QN;
end
end
endmodule




(b) JK Flip Flop

`timescale 1ns / 1ps
module JK_FF_74LS109(J,K_L,CLK,PR_L,CLR_L,Q,QN); input J,K_L,CLK,PR_L,CLR_L; output Q,QN;
wire W1,W2,W3,W4,W5,W6;
and x1(W1,J,CLR_L,W6,QN);
and x2(W2,K_L,CLR_L,Q);
nor x3(W3,W1,W2);
nand x4(W4,W5,W3,PR_L);

nand x5(W5,W4,CLR_L,CLK);
nand x6(W6,W5,CLK,W3);
nand x7(Q,QN,W5,PR_L);
nand x8(QN,Q,W6,CLR_L);
endmodule