Ripple Carry Adder RCA

Ripple Carry Adder : This means the carry is the ripple which is out from the first stage and used in the next stage ..

Block diagram of RCA is

Program Code :

`timescale 1ns / 1ps
module RCA(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
full_adder_behav1 u1(a[0],b[0],cin,s[0],c1);
full_adder_behav1 u2(a[1],b[1],c1,s[1],c2);
full_adder_behav1 u3(a[2],b[2],c2,s[2],c3);
full_adder_behav1 u4(a[3],b[3],c3,s[3],cout);
endmodule

module full_adder_behav1(a,b,cin,s,cout);
input a,b,cin;
output reg s,cout;
reg [2:0]d;
reg [1:0] s1;
always@*
begin
d[0]<=cin;
d[1]<=b;
d[2]<=a;
case(d)
3'b000: s1<=2'b00;
3'b001: s1<=2'b10;
3'b010: s1<=2'b10;
3'b011: s1<=2'b01;
3'b100: s1<=2'b10;
3'b101: s1<=2'b01;
3'b110: s1<=2'b01;
3'b111: s1<=2'b11;
default: s1<=2'b00;
endcase
s<=s1[1];
cout<=s1[0];
end
endmodule

Comments

Full Adder Using Multiplexer

Full Adder can be implemented by using mux .... These are the possible ways to do that !

Multiplexer and Demultiplexer

Multiplexer : 74 151 `timescale 1ns / 1ps module mux_74x151(EN_L, S, D, Y); input EN_L; input [2:0]S; input [7:0]D; output reg Y; reg y1; always@* begin case(S) 3'b000: y1<=D[0]; 3'b001: y1<=D[1]; 3'b010: y1<=D[2]; 3'b011: y1<=D[3]; 3'b100: y1<=D[4]; 3'b101: y1<=D[5]; 3'b110: y1<=D[6]; 3'b111: y1<=D[7]; default: y1<=1'b0; endcase if(EN_L==1'b0) Y<=y1; else Y<=1'b0; end endmodule Demultiplexer : 74 155 `timescale 1ns / 1ps module demux_74x155(ea,eab,ebb1,ebb2,A,outa,outb); input ea,eab,ebb1,ebb2; input [1:0]A; output reg [3:0]outa,outb; reg [3:0] y1; always@* begin case(A) 2'b00: y1<=4'b0111; 2'b01: y1<=4'b1011; 2'b10: y1<=4'b1101; 2'b11: y1<=4'b1110; default: y1<=4'b1111; endcase if(ea==1'b1 & eab==1'b0) outa <=y1; else outa <=4'b1111; if(ebb1==1'b0 & ebb2==1'b0) outb <=y1; else out...

Verilog programs

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