Ripple Carry Adder : This means the carry is the ripple which is out from the first stage and used in the next stage ..
Block diagram of RCA is
Program Code :
Block diagram of RCA is
Program Code :
`timescale 1ns / 1ps
module RCA(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
full_adder_behav1 u1(a[0],b[0],cin,s[0],c1);
full_adder_behav1 u2(a[1],b[1],c1,s[1],c2);
full_adder_behav1 u3(a[2],b[2],c2,s[2],c3);
full_adder_behav1 u4(a[3],b[3],c3,s[3],cout);
endmodule
module RCA(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
full_adder_behav1 u1(a[0],b[0],cin,s[0],c1);
full_adder_behav1 u2(a[1],b[1],c1,s[1],c2);
full_adder_behav1 u3(a[2],b[2],c2,s[2],c3);
full_adder_behav1 u4(a[3],b[3],c3,s[3],cout);
endmodule
module full_adder_behav1(a,b,cin,s,cout);
input a,b,cin;
output reg s,cout;
reg [2:0]d;
reg [1:0] s1;
always@*
begin
d[0]<=cin;
d[1]<=b;
d[2]<=a;
case(d)
3'b000: s1<=2'b00;
3'b001: s1<=2'b10;
3'b010: s1<=2'b10;
3'b011: s1<=2'b01;
3'b100: s1<=2'b10;
3'b101: s1<=2'b01;
3'b110: s1<=2'b01;
3'b111: s1<=2'b11;
default: s1<=2'b00;
endcase
s<=s1[1];
cout<=s1[0];
end
endmodule
input a,b,cin;
output reg s,cout;
reg [2:0]d;
reg [1:0] s1;
always@*
begin
d[0]<=cin;
d[1]<=b;
d[2]<=a;
case(d)
3'b000: s1<=2'b00;
3'b001: s1<=2'b10;
3'b010: s1<=2'b10;
3'b011: s1<=2'b01;
3'b100: s1<=2'b10;
3'b101: s1<=2'b01;
3'b110: s1<=2'b01;
3'b111: s1<=2'b11;
default: s1<=2'b00;
endcase
s<=s1[1];
cout<=s1[0];
end
endmodule
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