ALU

ALU :

Program Code :

`timescale 1ns / 1ps
module ALU74X181(M,S,A_L,B_L,CN,CN4,F_L,P_L,G_L,AEQB); input M,CN;
input [3:0]S,A_L,B_L;
output reg [3:0]F_L;
output reg CN4,P_L,G_L,AEQB;
reg [4:0]MS;
reg [3:0]F;
always@*
begin
MS<={M,S};
case(MS)
5'b00000: F_L<=A_L-1'b1;
5'b00001: F_L<=(A_L&B_L)-1'b1;
5'b00010: F_L<=(A_L&(~B_L))-1'b1;
5'b00011: F_L<=-1'b1;
5'b00100: F_L<=A_L+(A_L|(~B_L));
5'b00101: F_L<=(A_L&B_L)+(A_L|(~B_L));
5'b00110: F_L<=A_L-B_L-1'b1;
5'b00111: F_L<=A_L|(~B_L);
5'b01000: F_L<=A_L+(A_L|B_L);
5'b01001: F_L<=A_L+B_L;
5'b01010: F_L<=(A_L&(~B_L))+(A_L|B_L);
5'b01011: F_L<=A_L|B_L;
5'b01100: F_L<=A_L+A_L;
5'b01101: F_L<=(A_L&B_L)+A_L;
5'b01110: F_L<=(A_L&(~B_L))-A_L;
5'b01111: F_L<=A_L;
5'b10000: F_L<=~A_L;
5'b10001: F_L<=~(A_L&B_L);
5'b10010: F_L<=(~A_L)|(~B_L);
5'b10011: F_L<=4'b1111;
5'b10100: F_L<=(~A_L)|(~B_L);
5'b10101: F_L<=~B_L;
5'b10110: F_L<=(~A_L)^(~B_L);
5'b10111: F_L<=(A_L)|(~B_L);
5'b11000: F_L<=(~A_L)& (B_L);
5'b11001: F_L<=(A_L)^(B_L);
5'b11010: F_L<=B_L;
5'b11011: F_L<=(A_L)|(B_L);
5'b11100: F_L<=4'b0000;
5'b11101: F_L<=(A_L)&(~B_L);
5'b11110: F_L<=(A_L)&(B_L);
5'b11111: F_L<=A_L;
default: F_L<=4'bXXXX;
endcase

{CN4,F}<=(A_L+B_L)+CN;
P_L<=A_L^B_L;
G_L<=A_L&B_L;
if(A_L==B_L)
AEQB<=1'b1;
else
AEQB<=1'b0;
end
endmodule