Encoders : 74 148
Program Code :
module encoder74148(
input [7:0] I_L,
output reg [2:0] O_L,
input [0:0] EI,
output reg [0:0] EO_L,
output reg [0:0] GS
);
wire [7:0]I;
assign I=~I_L;
always @*
if(EI==0)
begin
if(I==8'b00000000)
begin
GS<=1'b1;
EO_L<=1'b0;
O_L<=3'b111;
end
if(I==8'b00000001)
O_L<=3'b111;
if(I>=8'b00000010&I<=00000011)
O_L <=3'b110;
if(I>=8'b00000100&I<=00000111)
O_L<=3'b101;
if(I>=8'b00001000&I<=00001111)
O_L<=3'b100;
if(I>=8'b00010000&I<=00011111)
O_L<=3'b011;
if(I>=8'b00100000&I<=00111111)
O_L<=3'b010;
if(I>=8'b01000000&I<=01111111)
O_L<=3'b001;
if(I>=8'b10000000&I<=11111111)
O_L<=3'b000;
GS<=1'b0;
EO_L<=1'b1;
End
else
begin
O_L<=3'b111;
GS<=1'b1;
EO_L<=1'b1;
End
endmodule
MODEL 2 :
`timescale 1ns / 1ps
module enc_74x148(EI_L,I_L,A_L,EO_L,GS_L);
input EI_L;
input [7:0]I_L;
output reg [2:0]A_L;
output reg GS_L,EO_L;
always@*
begin
if (EI_L==1'b1)
begin
A_L<=3'b111;
GS_L<=1'b1;
EO_L<=1'b1;
end
else
begin
GS_L<=1'b0;
EO_L<=1'b1;
if(I_L[7]==1'b0)
A_L<=3'b000;
else if(I_L[6]==1'b0)
A_L<=3'b001;
else if(I_L[5]==1'b0)
A_L<=3'b010;
else if(I_L[4]==1'b0)
A_L<=3'b011;
else if(I_L[3]==1'b0)
A_L<=3'b100;
else if(I_L[2]==1'b0)
A_L<=3'b101;
else if(I_L[1]==1'b0)
A_L<=3'b110;
else if(I_L[0]==1'b0)
A_L<=3'b111;
else
begin
GS_L<=1'b1;
EO_L<=1'b0;
A_L<=3'b111;
end
end
end
endmodule
Program Code :
module encoder74148(
input [7:0] I_L,
output reg [2:0] O_L,
input [0:0] EI,
output reg [0:0] EO_L,
output reg [0:0] GS
);
wire [7:0]I;
assign I=~I_L;
always @*
if(EI==0)
begin
if(I==8'b00000000)
begin
GS<=1'b1;
EO_L<=1'b0;
O_L<=3'b111;
end
if(I==8'b00000001)
O_L<=3'b111;
if(I>=8'b00000010&I<=00000011)
O_L <=3'b110;
if(I>=8'b00000100&I<=00000111)
O_L<=3'b101;
if(I>=8'b00001000&I<=00001111)
O_L<=3'b100;
if(I>=8'b00010000&I<=00011111)
O_L<=3'b011;
if(I>=8'b00100000&I<=00111111)
O_L<=3'b010;
if(I>=8'b01000000&I<=01111111)
O_L<=3'b001;
if(I>=8'b10000000&I<=11111111)
O_L<=3'b000;
GS<=1'b0;
EO_L<=1'b1;
End
else
begin
O_L<=3'b111;
GS<=1'b1;
EO_L<=1'b1;
End
endmodule
MODEL 2 :
`timescale 1ns / 1ps
module enc_74x148(EI_L,I_L,A_L,EO_L,GS_L);
input EI_L;
input [7:0]I_L;
output reg [2:0]A_L;
output reg GS_L,EO_L;
always@*
begin
if (EI_L==1'b1)
begin
A_L<=3'b111;
GS_L<=1'b1;
EO_L<=1'b1;
end
else
begin
GS_L<=1'b0;
EO_L<=1'b1;
if(I_L[7]==1'b0)
A_L<=3'b000;
else if(I_L[6]==1'b0)
A_L<=3'b001;
else if(I_L[5]==1'b0)
A_L<=3'b010;
else if(I_L[4]==1'b0)
A_L<=3'b011;
else if(I_L[3]==1'b0)
A_L<=3'b100;
else if(I_L[2]==1'b0)
A_L<=3'b101;
else if(I_L[1]==1'b0)
A_L<=3'b110;
else if(I_L[0]==1'b0)
A_L<=3'b111;
else
begin
GS_L<=1'b1;
EO_L<=1'b0;
A_L<=3'b111;
end
end
end
endmodule
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